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? semiconductor components industries, llc, 2004 march, 2004 ? rev. 1 1 publication order number: ncp1217/d ncp1217 enhanced pwm current-mode controller for high-power universal off-line supplies housed in an so?8 or pdip?7 package, the ncp1217 represents the enhanced version of the ncp1203?based controllers. thanks to its high drive capability, ncp1217 drives large gate?charge mosfets, which together with internal ramp compensation and built?in overvoltage protection, ease the design of modern ac/dc adapters. ncp1217 offers a true alternative to uc384x?based designs. with an internal structure operating at different fixed frequencies (65100133 khz), the controller features a high?voltage start?up fet, which ensures a clean and loss less start?up sequence. its current?mode control topology provides an excellent input audio? susceptibility and inherent pulse?by?pulse control. internal ramp compensation easily prevents subharmonic oscillations from taking place in continuous conduction mode designs. when the current setpoint falls below a given value, e.g. the output power demand diminishes, the ic automatically enters the so?called skip cycle mode and provides excellent efficiency at light loads. because this occurs at a user adjustable low peak current, no acoustic noise takes place. the ncp1217 features two efficient protective circuitries: 1) in presence of an overcurrent condition, the output pulses are disabled and the device enters a safe burst mode, trying to restart. once the default has gone, the device auto?recovers. 2) if an external signal (e.g. a temperature sensor) pulls pin1 above 3.2 v, output pulses are immediately stopped and the ncp1217 stays latched in this position. reset occurs when the v cc collapses to ground, e.g. the user unplugs the power supply. features ? current?mode with adjustable skip?cycle capability ? built?in internal ramp compensation ? auto?recovery internal output short?circuit protection ? full latch?off if adjustment pin is brought high ? extremely low no?load standby power ? internal temperature shutdown ? 500 ma peak current capability ? fixed frequency versions at 65 khz, 100 khz and 133 khz ? direct optocoupler connection ? internal leading edge blanking ? spice models available for transient and ac analysis typical applications ? high power ac/dc converters for tvs, set?top boxes, etc. ? offline adapters for notebooks ? telecom dc?dc converters ? all power supplies pdip?7 p suffix case 626b 1 8 1 8 so?8 d suffix case 751 18 5 3 4 (top view) adj cs hv pin connections 7 6 2 nc fb gnd drv v cc marking diagrams see detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. ordering information xxx = device code: 065, 100 or 133 yy = device code: 06 for 65 10 for 100 13 for 133 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week http://onsemi.com 17dyy alyw 1 8 p1217pxxx awl yyww 1 miniature pwm controller for high power ac/dc wall adapters and offline battery chargers
ncp1217 http://onsemi.com 2 figure 1. typical application example emi filter universal input + + ncp1217 + v out aux. adj fb cs gnd hv v cc drv 1 2 3 4 8 7 6 5 ramp adjustment see application section pin function description pin no. pin name function description 1 adj adjust the skipping peak current this pin lets you adjust the level at which the cycle skipping process takes place. shorting this pin to ground permanently disables the skip cycle feature. by bringing this pin above 3.1 v, you permanently shut off the device. 2 fb sets the peak current setpoint by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 cs current sense input this pin senses the primary current and routes it to the internal comparator via an l.e.b. by inserting a resistor in series with the pin, you control the amount of ramp compensation you need. 4 gnd the ic ground ? 5 drv driving pulses the driver's output to an external mosfet. 6 v cc supplies the ic this pin is connected to an external bulk capacitor of typically 22 f. 7 nc ? this unconnected pin ensures adequate creepage distance. 8 hv ensures a clean and lossless start?up sequence connected to the high?voltage rail, this pin injects a constant current into the v cc capacitor during the start?up sequence.
ncp1217 http://onsemi.com 3 figure 2. internal circuit architecture overload management uvlo high and low 500 ma hv current source internal v cc 8 7 6 5 hv nc v cc drv 1 2 3 4 q flip?flop dcmax = 74% q 250 ns l.e.b. 65?100?133 khz clock - + - + 80 k 20 k 57 k 1 v current sense ground fb adj 24 k 25 k + ? v ref reset 1.1 v skip cycle comparator set 19 k ramp compensation reset - + latch?off comparator + ? latch reset set 3.1 v uvlo maximum ratings rating symbol value unit power supply voltage v cc 16 v power supply voltage on all other pins except pin 8 (hv), pin 6 (v cc ) and pin 5 (drv) ? ?0.3 to 10 v maximum voltage on pin 8 (hv), pin 6 (v cc ) decoupled to ground with 10 f v hv 500 v maximum voltage on pin 8 (hv), pin 6 (v cc ) grounded v hv 450 v maximum current into all pins except v cc (6) and hv (8) when 10 v esd diodes are activated ? 5.0 ma thermal resistance, junction?to?case r q j?c 57 c/w thermal resistance, junction?to?air, pdip?7 version thermal resistance, junction?to?air, so?8 version r q j?a r q j?a 100 178 c/w maximum junction temperature t jmax 150 c temperature shutdown ? 155 c hysteresis in shutdown ? 30 c storage temperature range ? ?60 to +150 c esd capability, hbm model (all pins except v cc and hv) ? 2.0 kv esd capability, machine model ? 200 v
ncp1217 http://onsemi.com 4 electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 11 v unless otherwise noted.) characteristic pin symbol min typ max unit supply section (all frequency versions, unless otherwise noted) turn?on threshold level, v cc going up 6 vcc on 11.8 12.8 13.8 v minimum operating voltage after turn?on 6 vcc min 6.9 7.6 8.3 v v cc decreasing level at which the latch?off phase ends 6 vcc latch ? 5.6 ? v internal ic consumption, no output load on pin 5, f sw = 65 khz 6 icc1 ? 960 1110 (note 1) a internal ic consumption, no output load on pin 5, f sw = 100 khz 6 icc1 ? 1020 1180 (note 1) a internal ic consumption, no output load on pin 5, f sw = 133 khz 6 icc1 ? 1060 1200 (note 1) a internal ic consumption, 1.0 nf output load on pin 5, f sw = 65 khz 6 icc2 ? 1.7 2.0 (note 1) ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 100 khz 6 icc2 ? 2.1 2.4 (note 1) ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 133 khz 6 icc2 ? 2.4 2.9 (note 1) ma internal ic consumption, latch?off phase, v cc = 6.0 v 6 icc3 ? 230 ? a internal start?up current source (t j 0 c) high?voltage current source, v cc = 10 v 8 ic1 3.5 (note 2) 6.0 7.8 ma high?voltage current source, v cc = 0 8 ic2 ? 7.0 ? ma drive output output voltage rise?time @ cl = 1.0 nf, 10?90% of a 12 v output signal 5 t r ? 60 ? ns output voltage fall?time @ cl = 1.0 nf, 10?90% of a 12 v output signal 5 t f ? 20 ? ns source resistance 5 r oh 15 20 35 sink resistance 5 r ol 5.0 10 18 current comparator (pin 5 unloaded) input bias current @ 1.0 v input level on pin 3 3 i ib ? 0.02 ? a maximum internal current setpoint 3 i limit 0.9 1.0 1.1 v default internal current setpoint for skip cycle operation 3 i lskip ? 330 ? mv propagation delay from current detection to gate off state 3 t del ? 90 150 ns leading edge blanking duration 3 t leb ? 250 ? ns internal oscillator (v cc = 11 v, pin 5 loaded by 1.0 k ) oscillation frequency, 65 khz version ? f osc 58.5 65 71.5 khz oscillation frequency, 100 khz version ? f osc 90 100 110 khz oscillation frequency, 133 khz version ? f osc 120 133 146 khz maximum duty?cycle, ncp1217 ? dmax 69 74 80 % 1. maximum value @ t j = 0 c. 2. minimum value @ t j = 125 c.
ncp1217 http://onsemi.com 5 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 11 v unless otherwise noted.) characteristic pin symbol min typ max unit feedback section (v cc = 11 v, pin 5 loaded by 1.0 k ) internal pull?up resistor 2 rup ? 19 ? k pin 2 (fb) to internal current setpoint division ratio ? iratio ? 3.3 ? ? skip cycle generation default skip mode level 1 vskip 0.93 1.1 1.26 v pin 1 internal output impedance 1 zout ? 27 ? k w internal ramp compensation internal ramp level @ 25 c (note 3) 3 vramp 2.6 2.9 3.2 v internal ramp resistance to cs pin 3 rramp ? 19 ? k w adjustment latch?off level latching level 1 vlatch 2.69 3.10 3.42 v 3. a 1.0 m resistor is connected to the ground for the measurement. typical characteristics ?25 60 50 20 25 0 hv pin leakage current @ 500v ( m a) 0 temperature ( c) 80 temperature ( c) 10 40 50 125 icc1, ( m a) 900 figure 3. high voltage pin leakage current vs. temperature figure 4. vcc off vs. temperature figure 5. vcc min vs. temperature figure 6. icc1 (@ v cc =11v) vs. temperature temperature ( c) 1100 500 1200 75 100 ?25 13.5 50 12.0 25 0 vcc off , (v) 11.0 14.0 11.5 12.5 13.0 125 75 100 ?25 50 25 0 vcc min , (v) 7.0 9.0 temperature ( c) 7.5 8.0 8.5 125 75 100 ?25 50 25 0 125 75 100 700 800 1000 600 70 30 65 khz 100 khz 133 khz
ncp1217 http://onsemi.com 6 typical characteristics (continued) ?25 5.80 50 5.50 25 0 vcc latch , (v) 5.30 temperature ( c) 5.90 temperature ( c) 5.40 5.60 5.70 125 temperature ( c) 75 100 ?25 50 300 25 0 icc3, ( m a) 200 400 250 350 125 75 100 ?25 25 50 10 25 0 driver resistance , ( ) 0 30 temperature ( c) 5 15 20 125 75 100 source sink ?25 1.05 50 0.95 25 0 current sense limit , (v) 0.90 1.10 1.00 125 75 100 figure 7. icc2 vs. temperature temperature ( c) figure 8. switching frequency vs. temperature temperature ( c) ?25 2.40 50 1.60 25 0 i cc2 , (ma) 1.00 2.80 1.20 1.80 2.00 125 75 100 2.60 ?25 130 50 25 0 f osc , (khz) 50 150 70 90 110 125 75 100 1.40 2.20 figure 9. vcc latch vs. temperature figure 10. icc3 vs. temperature figure 11. drive sink and source resistance vs. temperature figure 12. current sense limit vs. temperature 65 khz 100 khz 133 khz 65 khz 100 khz 133 khz
ncp1217 http://onsemi.com 7 typical characteristics (continued) duty cycle, (%) figure 13. vskip vs. temperature figure 14. max duty?cycle vs. temperature temperature ( c) 80 70 ?25 1.15 50 1.05 25 0 vskip , (v) 1.00 1.20 temperature ( c) 1.10 125 75 100 50 25 ?25 125 75 100 76 78 74 0 72 vramp, (v) temperature ( c) temperature ( c) figure 15. vramp vs. temperature figure 16. high voltage current source (@ vcc=10v) vs. temperature ?25 50 5.0 25 0 ic1, (ma) 3.0 8.0 4.0 6.0 7.0 125 75 100 ?25 3.00 50 2.80 25 0 2.70 3.10 2.75 2.90 125 75 100 3.05 2.85 2.95
ncp1217 http://onsemi.com 8 application information introduction the ncp1217 implements a standard current mode architecture where the switch?off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part?count is the key parameter, particularly in low?cost ac/dc adapters, tv power supplies, etc. due to its high?performance high?voltage technology, the ncp1217 incorporates all the necessary components normally needed in uc384x based supplies: timing components, feedback devices, low?pass filter and start?up device but also enhances the original component by offering: 1) an externally triggerable latch?off 2) ramp compensation and finally, 3) short?circuit protection. due to its high?voltage current source, on semiconductor's ncp1217 does not need an external start?up resistance but supplies the start?up current directly from the high?voltage rail. on the other hand, more and more applications are requiring low no?load standby power, e.g. for ac/dc adapters, vcrs, etc. uc384x series have a lot of difficulty to reduce the switching losses at low power levels. ncp1217 elegantly solves this problem by skipping unwanted switching cycles at a user?adjustable power level. by ensuring that skip cycles take place at low peak current, the device ensures quiet, noise?free operation: current?mode operation: as the uc384x series, the ncp1217 features a well?known current mode control architecture which provides superior input audio? susceptibility compared to traditional voltage?mode controllers. primary current pulse?by?pulse checking together with a fast over current comparator offers greater security in the event of a difficult fault condition, e.g. a saturating transformer. ramp compensation: by inserting a resistor between the current?sense (cs) pin and the actual sense resistor, it becomes possible to inject a given amount of ramp compensation since the internal saw tooth clock is routed to the cs pin. subharmonic oscillations in continuous conduction mode (ccm) can thus be compensated via a single resistor. adjustable skip cycle level: by offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. this point guarantees a noise?free operation with cheap transformers. skip cycle offers a proven mean to reduce the standby power in no or light loads situations. wide switching?frequency offer: three different options are available: 65 khz100 khz133 khz. depending on the application, the designer can pick up the right device to help reducing magnetics or improve the emi signature before reaching the 150 khz starting point. over current protection (ocp): by continuously monitoring the vcc auxiliary winding voltage, ncp1217 enters burst mode as soon as the power supply undergoes an overload: when the vcc voltage goes down until it crosses the undervoltage lockout level (vccmin). when the ncp1217 reaches this level (typically 7.6 v), it stops the switching pulses until the vcc pin voltage reaches vcclatch (5.6 v). at vcclatch, the ncp1217 attempts to restart. as soon as the default disappears, the power supply resumes operation. over voltage protection (ovp): if pin1 is brought to a level higher than the internal 3.2 v reference voltage, the controller is permanently shut down until the user cycles the v cc off and on again. this allows the building of ef ficient and low?cost over voltage protection circuits. wide duty?cycle operation: wide mains operation requires a large duty?cycle excursion. the ncp1217 can go up to 74% typically. low standby?power: if smps naturally exhibit a good efficiency at nominal load, they begin to be less efficient when the output power demand diminishes. by skipping unneeded switching cycles, the ncp1217 drastically reduces the power wasted during light load conditions. in no?load conditions, the npc1217 allows the total standby power to easily reach next international energy agency (iea) recommendations. no acoustic noise while operating: instead of skipping cycles at high peak currents, the ncp1217 waits until the peak current demand falls below a user?adjustable 1/3 of the maximum limit. as a result, cycle skipping can take place without having a singing transformer you can thus select cheap magnetic components free of noise problems. external mosfet connection: by leaving the external mosfet external to the ic, you can select avalanche proof devices, which in certain cases (e.g. low output powers), let you work without an active clamping network. also, by controlling the mosfet gate signal flow, you have an option to slow down the device commutation, therefore reducing the amount of electromagnetic interference (emi). spice model: a dedicated model to run transient cycle?by?cycle simulations is available but also an averaged version to help you closing the loop. ready?to?use templates can be downloaded in orcad's pspice and intusoft's isspice from on semiconductor web site, ncp1217 related section.
ncp1217 http://onsemi.com 9 start?up sequence when the power supply is first powered from the mains outlet, the internal current source (typically 7.0 ma) is biased and charges up the v cc capacitor. when the voltage on this v cc capacitor reaches the vcc on level (typically 12.8 v), the current source turns off and no longer wastes any power. at this time, the v cc capacitor only supplies the controller and the auxiliary supply is supposed to take over before v cc collapses below vcc min . figure 17 shows the internal arrangement of this structure. figure 17. the current source brings v cc above 12.8 v and then turns off - + 8 6 4 6 ma or 0 cv cc aux hv 12.8 v/5.6 v once the power supply has started, the v cc shall be constrained below 16 v, which is the maximum rating on pin 6. figure 18 portrays a typical start?up sequence with a v cc regulated at 12.5 v. figure 18. a typical start?up sequence for the ncp1217 t, time (sec) 3.00 m 8.00 m 13.0 m 18.0 m 23.0 m 13.5 12.5 11.5 10.5 9.5 regulation 12.8 v overload operation in applications where the output current is purposely not controlled (e.g. wall adapters delivering raw dc level), it is interesting to implement a true short?circuit protection. a short?circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler led. as a result, the auxiliary voltage also decreases because it also operates in flyback and thus duplicates the output voltage, providing the leakage inductance between windings is kept low. to account for this situation and properly protect the power supply, ncp1217 hosts a dedicated overload detection circuitry. once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty?cycle. the system auto?recovers when the fault condition disappears. during the start?up phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. the auxiliary voltage takes place after a few switching cycles and self?supplies the ic. in presence of a short circuit on the output, the auxiliary voltage will go down until it crosses the undervoltage lockout level of typically 7.6 v. when this happens, ncp1217 immediately stops the switching pulses and unbiases all unnecessary logical blocks. the overall consumption drops, while keeping the gate grounded, and the v cc slowly falls down. as soon as v cc reaches typically 5.6 v, the start?up source turns?on again and a new start?up sequence occurs, bringing v cc toward 12.8 v as an attempt to restart. if the default has gone, then the power supply normally restarts. if not, a new protective burst is initiated, shielding the smps from any runaway. figure 19 portrays the typical operating signals in short circuit.
ncp1217 http://onsemi.com 10 figure 19. typical waveforms in short circuit conditions vcc on = 12.8 v v cc driving pulses vcc min = 7.6 v vcc latch = 5.6 v calculating the v cc capacitor the v cc capacitor can be calculated knowing the ic consumption as soon as v cc reaches 12.8 v. suppose that a ncp1217p065 is used and drives a mosfet with a 30 nc total gate charge (qg). the total average current is thus made of icc1 (750 a) plus the driver current, fsw * qg 1.95 ma . the total current is therefore 2.7 ma. the v available to fully start?up the circuit (e.g. never reach the 8.2 v vcc min during power on) is 13.7?8.2 5.5 v best case or 4.9 v worse case (11.9?7.0) . we have a capacitor that then needs to supply the ncp1217 with 2.7 ma during a given time until the auxiliary supply takes over. suppose that this time was measured at around 15 ms. cv cc is calculated using the equation c ti v or c 8.3 f. select a 22 f/25 v and this will fit. skipping cycle mode the ncp1217 automatically skips switching cycles when the output power demand drops below a given level. this is accomplished by monitoring the fb pin. in normal operation, pin 2 imposes a peak current accordingly to the load value. if the load demand decreases, the internal loop asks for less peak current. when this setpoint reaches a determined level (vpin 1), the ic prevents the current from decreasing further down and starts to blank the output pulses: the ic enters the so?called skip cycle mode, also named controlled burst operation. the power transfer now depends upon the width of the pulse bunches (figure 21). suppose we have the following component values: lp, primary inductance = 350 h fsw, switching frequency = 65 khz ip skip = 600 ma (or 333 mv/rsense) the theoretical power transfer is therefore: 1 2 lpip 2 fsw 4.1 w . if this ic enters skip cycle mode with a bunch length of 10 ms over a recurrent period of 100 ms, then the total power transfer is: 4.1 * 0.1 410 mw . to better understand how this skip cycle mode takes place, a look at the operation mode versus the fb level immediately gives the necessary insight. figure 20. skip cycle operation i p(min) = 333 mv/r sense normal current mode operation fb 1 v 4.2 v, fb pin open 3.2 v, upper dynamic range time when fb is above the skip cycle threshold (1.0 v by default), the peak current cannot exceed 1.0 v/rsense. when the ic enters the skip cycle mode, the peak current cannot go below vpin1/3.3. the user still has the flexibility to alter this 1.0 v by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. in this later case, care must be taken to keep suf ficient margin between this pin 1 adjustment level and the latch?off level. grounding pin 1 permanently invalidates the skip cycle operation.
ncp1217 http://onsemi.com 11 power p1 power p2 power p3 figure 21. output pulses at various power levels (x = 5.0 s/div) p1 p2 p3 figure 22. the skip cycle takes place at low peak currents which guarantees noise?free operation 315.40 u 882.70 u 1.450 m 2.017 m 2.585 m 300 m 200 m 100 m 0 max peak current skip cycle current limit sufficient margin shall be kept between normal pin1 level and the latch?off point in order to avoid false triggering. ramp compensation ramp compensation is a known mean to cure subharmonic oscillations. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty?cycle greater than 50%. to lower the current loop gain, one usually injects between 50 and 100% of the inductor down?slope. figure 23 depicts how internally the ramp is generated.
ncp1217 http://onsemi.com 12 f igure 23. inserting a resistor in series with the curren t sense information brings ramp compensation + - from setpoint l.e.b. 19 k cs rcomp rsense 2.9 v 0 v duty cycle typ = 74% in the ncp1217, the ramp features a swing of 2.9 v with a duty cycle max at 74%. over a 65 khz frequency, for instance, it corresponds to a 254 mv/ s ramp. in our flyback design, let's suppose that our primary inductance lp is 350 h, delivering 12 v with a np:ns ratio of 1:0.1. the off time primary current slope is thus given by: (vout vf) np ns lp 371 ma s or 37 mv s when projected over an rsense of 0.1 , for instance. if we select 75% of the downslope as the required amount of ramp compensation, then we shall inject 27 mv/ s. our internal compensation being of 254 mv/ s, the divider ratio ( divratio ) between rcomp and the 19 k is 0.106. a few lines of algebra to determine rcomp: 19 k divratio (1?divratio) 2.26 k . latching off the ncp1217 total latched shutdown can easily be implemented through a simple pnp bipolar transistor as depicted by figure 24. when off, q1 is transparent to the operation. when forward biased, the transistor pulls the adj pin toward v cc and permanently latches?off the ic as soon vadj goes above the latching level (typical 3.1 v). figure 24 shows how to wire the bipolar transistor to activate the latch?off. a typical candidate for q1 could be an mmbt3906 from on semiconductor. figure 24. a simple bipolar transistor totally disables the ic cv cc 8 7 6 5 1 2 3 4 off v cc q1 rlimit figure 25. when vadj is pulled above 3.1 v, ncp1217 permanently latches?off the output pulses default adj level fault brings adj above latching level latched?off reset level the start?up current source keeps the device latched until reset occurs. v cc time time time driver pulses drv adj vcc on = 12.8 v vcc min = 7.6 v vcc latch = 5.6 v
ncp1217 http://onsemi.com 13 in normal operation, the adj pin level is kept at a fixed level, the default one or lower. as soon as some external signal pulls this adj pin level above 3.1 v typical, the output pulses are permanently disabled. care must be taken to limit the injected current into pin 1 to less than 2.0 ma, e.g. through a series resistor of 5.6 k with a 10 v v cc . the start?up switch is activated every time v cc reaches 5.6 v and maintains a v cc voltage ramping up and down between 5.6 v and 12.8 v. reset occurs when v cc falls below 5.6 v, e.g. when the user cycle the smps down. figure 26 illustrates the operation. adding a zener diode from q1 base to ground makes a cheap ovp, protecting the supply from any lethal open?loop operation. if a thermistor (ntc) is added in parallel with the zener?diode, overtemperature protection is also ensured. figure 26. a thermistor and a zener diode offer both ovp and overtemperature latched?off protection laux 8 7 6 5 1 2 3 4 vaux cv cc 16 v ovp t non?latching shutdown in some cases, it might be desirable to shut off the part temporarily and authorize its restart once the default has disappeared. this option can easily be accomplished through a single npn bipolar transistor wired between fb and ground. by pulling fb below the adj pin 1 level, the output pulses are disabled as long as fb is pulled below pin 1. as soon as fb is relaxed, the ic resumes its operation. figure 27 depicts the application example. figure 27. another way of shutting down the ic without a definitive latch?off state 8 7 6 5 1 2 3 4 q1 on/off protecting the controller against negative spikes as with any controller built upon a cmos technology, it is the designer's duty to avoid the presence of negative spikes on sensitive pins. negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. sometimes, the injection can be so strong that internal parasitic scrs are triggered, engendering irremediable damages to the ic if a low impedance path is offered between v cc and gnd. if the current sense pin is often the seat of such spurious signals, the high?voltage pin can also be the source of problems in certain circumstances. during the turn?off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its v cc capacitor and keeps activating the mosfet on and off with a peak current limited by rsense. unfortunately, if the quality coefficient q of the resonating network formed by lp and cbulk is low (e.g. the mosfet rdson + rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. since we are talking about ms pulses, the amount of injected charge (q = i * t) immediately latches the controller that brutally discharges its v cc capacitor. if this v cc capacitor is of sufficient value, its stored energy damages the controller. figure 28 depicts a typical negative shot occurring on the hv pin where the brutal v cc discharge testifies for latch?up.
ncp1217 http://onsemi.com 14 figure 28. a negative spike takes place on the bulk capacitor at the switch?off sequence vcc 5 v/div vlatch 1 v/div time 10 ms/div simple and inexpensive cures exist to prevent from internal parasitic scr activation. one of them consists in inserting a resistor in series with the high?voltage pin to keep the negative current to the lowest when the bulk becomes negative (figure 29). please note that the negative spike is clamped to (?2*vf) thanks to the diode bridge. also, the power dissipation of this resistor is extremely small since it only heats up during the startup sequence. another option (figure 30) consists in wiring a diode from v cc to the bulk capacitor to force v cc to reach vcc on sooner and thus stops the switching activity before the bulk capacitor gets deeply discharged. for security reasons, two diodes can be connected in series. figure 29. a simple resistor in series avoids any latch?up in the controller . . . figure 30. . . . or one diode forces v cc to reach vcc on sooner. 8 7 6 5 1 2 3 4 + cbulk rbulk 4.7 k + cv cc 1 3 2 8 7 6 5 1 2 3 4 + cbulk + d3 1n4007 cv cc 1 3
ncp1217 http://onsemi.com 15 ordering information device version marking package shipping ncp1217p065 65 khz p1217p065 pdip?7 50 units/rail NCP1217D065 65 khz 17d06 so?8 2500 units/reel ncp1217p100 100 khz p1217p100 pdip?7 50 units/rail ncp1217d100 100 khz 17d10 so?8 2500 units/reel ncp1217p133 133 khz p1217p133 pdip?7 50 units/rail ncp1217d133 133 khz 17d13 so?8 2500 units/reel
ncp1217 http://onsemi.com 16 package dimensions so?8 d suffix case 751?07 issue aa seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751-01 thru 751-06 are obsolete. new standard is 751-07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m
ncp1217 http://onsemi.com 17 package dimensions pdip?7 p suffix case 626b?01 issue a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension l to center of lead when formed parallel. 4. package contour optional (round or square corners). 5. dimensions a and b are datums. 14 5 8 f note 2 ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max millimeters a 9.40 10.16 b 6.10 6.60 c 3.94 4.45 d 0.38 0.51 f 1.02 1.78 g 2.54 bsc h 0.76 1.27 j 0.20 0.30 k 2.92 3.43 l 7.62 bsc m ??? 10 n 0.76 1.01 a b
ncp1217 http://onsemi.com 18 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp1217/d the product described herein (ncp1217), may be covered by the following u.s. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,70 9, 6,587,357. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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